The Si5317 effectively removes unwanted noise on any clock frequency from 1 to 710 MHz and produces two ultra-low jitter output clocks at the same frequency as the input.
Online PR News – 03-November-2010 – – AUSTIN, Texas, June 14, 2010 - Silicon Laboratories Inc. (NASDAQ: SLAB), a leader in high-performance, analog-intensive, mixed-signal ICs, today announced the industry’s most frequency-flexible timing IC solution for networking and telecommunications applications that require jitter attenuation for clock signals without clock multiplication. Silicon Labs’ new Si5317 pin-controlled jitter cleaning clock IC provides jitter filtering to remove unwanted noise and produces low jitter outputs for a wide range of applications such as wireless backhaul equipment, DSLAMs, multi-service access nodes (MSANs), GPON/EPON optical line termination (OLT) line cards, and 10 GbE switches and routers.
As networking and telecom hardware designs migrate to higher speeds and greater complexity, timing architecture has become a key consideration in the overall system design. Managing clock jitter is especially critical in high-speed applications since this noise degrades overall system performance, impacting the design’s bit-error-rate (BER) and signal-to-noise ratio (SNR). The Si5317 clock cleaner provides a simple, flexible and cost-effective jitter filtering solution for these performance-sensitive applications.
The Si5317 effectively removes unwanted noise on any clock frequency from 1 to 710 MHz and produces two ultra-low jitter output clocks at the same frequency as the input. Unlike traditional clock ICs or discrete phase-locked loop (PLL) module solutions requiring multiple components to support different frequencies, one Si5317-based design and layout supports jitter attenuation for any